Semiconductors are generally used in integrated circuits for a wide range of electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. Over the years of development of integrated circuits, the structures used to form the integrated circuit elements such as transistors and diodes have been continually reduced in size to enable production of ever more complex devices in small sizes, with improved performance, and with low cost. An example of a highly integrated semiconductor device is a dynamic random access memory (DRAM) device in which a large number of transistors are configured to store a substantial amount of digital information in a very compact size with relatively low cost.
One type of DRAM is a double data rate (DDR) synchronous dynamic random access memory (SDRAM). Double data rate memories use a differential clock signal that is carried over two lines, where each line carries complement of the other line. Output data from the memory are aligned to the rising and falling edge of both clocks lines. Therefore, the duty cycle of the differential clock directly affects the output data window.
FIG. 1 shows a timing diagram of the output data window as compared with the differential clock. As noted in the figure, the differential clock includes two complementary components, labeled CLK and bCLK (sometimes called “clock bar”). The output data is labeled DATA_OUT. The chart shows three time periods: tCK is the cycle time of CLK and bCLK; tDT is the time from the rising edge of CLK to the rising edge of bCLK; and tbDT is the time from the rising edge of bCLK to the rising edge of CLK. From these time periods, two duty cycles can be computed. In particular, the duty cycle of CLK can be computed as tDT/tCK and the duty cycle of bCLK can be computed as tbDT/tCK.
The duty cycle of the differential clock that includes CLK and bCLK is critical to the setup/hold time of the device receiving the data. In general, while it is desirable to have a 50% duty cycle, the differential clock provided to a DRAM can have some range of duty cycle distortion for the data interface. As the clock frequency becomes higher (i.e., as tCK becomes smaller), the duty cycle distortion becomes more critical. Consequently, a high-end memory device includes an on-chip duty cycle corrector (DCC).
A number of analog DCCs have been developed for fast operating chips such as microprocessors and graphics memories. An analog DCC, however, is not suitable for commodity memory chips since it is very difficult to save power consumption during the power saving mode. In general, an analog DCC uses the difference of accumulated charges between the two clock lines. Unfortunately, it is very difficult to keep the accumulated charges for a long time without updating. Therefore, even if a memory chip is in a power saving mode, the clock should be provided to the DCC in order to keep the accumulated charges. This means that neither the clock buffers nor the DCC can be disabled during the power saving mode. Consequently, the chip continuously consumes power even during the power saving mode.